Ping_Pong_Precise_Timing

  • user warning: Can't open file: 'cache.MYI' (errno: 145) query: SELECT data, created, headers, expire, serialized FROM cache WHERE cid = 'schema' in /var/www/vhosts/mattalltech.com/httpdocs/includes/cache.inc on line 26.
  • user warning: Can't open file: 'cache.MYI' (errno: 145) query: UPDATE cache SET data = 'a:50:{s:6:\"blocks\";a:7:{s:11:\"description\";s:62:\"Stores block settings, such as region and visibility settings.\";s:6:\"fields\";a:13:{s:3:\"bid\";a:3:{s:4:\"type\";s:6:\"serial\";s:8:\"not null\";b:1;s:11:\"description\";s:29:\"Primary Key: Unique block ID.\";}s:6:\"module\";a:5:{s:4:\"type\";s:7:\"varchar\";s:6:\"length\";i:64;s:8:\"not null\";b:1;s:7:\"default\";s:0:\"\";s:11:\"description\";s:126:\"The module from which the block originates; for example, \'user\' for the Who\'s Online block, and \'block\' for any custom blocks.\";}s:5:\"delta\";a:5:{s:4:\"type\";s:7:\"varchar\";s:6:\"length\";i:32;s:8:\"not null\";b:1;s:7:\"default\";s:1 in /var/www/vhosts/mattalltech.com/httpdocs/includes/cache.inc on line 109.
  • user warning: Can't open file: 'cache.MYI' (errno: 145) query: SELECT data, created, headers, expire, serialized FROM cache WHERE cid = 'theme_registry:mattalltech' in /var/www/vhosts/mattalltech.com/httpdocs/includes/cache.inc on line 26.
  • user warning: Can't open file: 'cache.MYI' (errno: 145) query: UPDATE cache SET data = 'a:127:{s:24:\"block_admin_display_form\";a:7:{s:8:\"template\";s:38:\"modules/block/block-admin-display-form\";s:4:\"file\";s:29:\"modules/block/block.admin.inc\";s:9:\"arguments\";a:1:{s:4:\"form\";N;}s:4:\"type\";s:6:\"module\";s:10:\"theme path\";s:13:\"modules/block\";s:11:\"theme paths\";a:1:{i:0;s:13:\"modules/block\";}s:20:\"preprocess functions\";a:2:{i:0;s:19:\"template_preprocess\";i:1;s:44:\"template_preprocess_block_admin_display_form\";}}s:17:\"color_scheme_form\";a:6:{s:9:\"arguments\";a:1:{s:4:\"form\";N;}s:4:\"type\";s:6:\"module\";s:10:\"theme path\";s:13:\"modules/color\";s:8:\"function\";s:23:\"theme_color_scheme_form\";s:11:\"theme paths\";a in /var/www/vhosts/mattalltech.com/httpdocs/includes/cache.inc on line 109.
  1. *************************************************************************
  2. * Program for Running Light on LED Row of Dragon 12 Eval Board *
  3. * LED Row is connected to PORT B *
  4. * To turn on the port B LEDs, PJ1 must be an output & set for logic 0 *
  5. * The lower 4 bits of Port P control the LED mutiplexing (neg. Logic) *
  6. * The common bus for the 7 Segment LEDs is also connected to Port B *
  7. * To avoid turning on Segments on the LEDs, all Digits are turned off *
  8. * Written for Dragon 12 Eval Board *
  9. * Written for MiniIde Assembler, Sep. 23, 2008, by Dr.M. Giesselmann *
  10. *************************************************************************
  11.  
  12. PORTB EQU $01 ;Port B I/O Data Register
  13. DDRB EQU $03 ;Port B Data Direction Register
  14.  
  15. PTP EQU $258 ;Port P I/O Data Register
  16. DDRP EQU $25A ;Port P Data Direction Register
  17. PTJ EQU $268 ;Port J I/O Data Register
  18. DDRJ EQU $26A ;Port J Data Direction Register
  19.  
  20. DELAY EQU 125 ;Define Delay in ms for Animation Speed
  21.  
  22. *************************************
  23. * Register Constants (Clock) *
  24. *************************************
  25. Eclock EQU 24000000 ;24 MHz CPU Frequency
  26. Loops1ms EQU (Eclock/6/1000)-4;Number of Loops for 1.0ms @ 6 cycles per loop
  27. * ;Reduce Number of Loops by 2&2 for Overhead
  28.  
  29. ************************************
  30. * Start (ORIGIN) of Code in Memory *
  31. ************************************
  32. ORG $1000 ;Origin=Bottom of RAM
  33. *************************
  34. * User Code starts here *
  35. *************************
  36. Init: BSET DDRP, $0F ;Make Low Nibble of Port P all Outputs
  37. BSET PTP, $0F ;Turn all LED Digits off
  38. MOVB #$FF, DDRB ;Make all Bits of Port B Outputs
  39. MOVB #$80, PORTB ;Turn on MSB LED on PORT B
  40. BSET DDRJ, #$02 ;Make Bit 2 of Port J Output
  41. BCLR PTJ, #$02 ;Enable LED Row
  42.  
  43. Right: LSR PORTB ;Right Shift Bits in PORT B
  44. BSR TimDel ;Call Time Delay Subroutine
  45. LDAA PORTB ;Load Accu A with contents of PORT B
  46. CMPA #$01 ;Compare with BitMask %0000,0001
  47. BNE Right ;Continue to Shift Right if LSB not reached
  48.  
  49. Left: LSL PORTB ;Left Shift Bits in PORT B
  50. BSR TimDel ;Call Time Delay Subroutine
  51. LDAA PORTB ;Load Accu A with contents of PORT B
  52. CMPA #$80 ;Compare with BitMask %1000,0000
  53. BNE Left ;Continue to Shift Right if MSB not reached
  54.  
  55. BRA Right ;Start back at the Beginning
  56.  
  57. *********************************************************
  58. * Time Delay Subroutine, 12 Cycles Overhead inner loop *
  59. *********************************************************
  60. TimDel: PSHX ;Push X onto stack to preserve it, 2 Cycles
  61. LDX #DELAY ;Load X with number of Loops for 1ms, 2 Cycles
  62. Loop: BSR OneMS ;Call 1ms Delay Routine, 4 cycles
  63. NOP ;No Operation, padd loop with 1 cycle
  64. NOP ;No Operation, padd loop with 1 cycle
  65. NOP ;No Operation, padd loop with 1 cycle
  66. NOP ;No Operation, padd loop with 1 cycle
  67. NOP ;No Operation, padd loop with 1 cycle
  68. DBNE X, Loop ;Decrement X and Branch to LoopX if X>0, 3 cycles
  69. PULX ;Restore X from Stack, 3 Cycles
  70. RTS ;Return from Time Delay Subroutine, 5 Cycles
  71.  
  72. *********************************************************
  73. * 1.0 ms Time Delay Subroutine, 12 Cycles Overhead *
  74. *********************************************************
  75. OneMS: PSHX ;Push X onto stack to preserve it, 2 Cycles
  76. LDX #Loops1ms ;Load X with number of Loops for 1ms, 2 Cycles
  77. LoopX: NOP ;No Operation, padd loop with 1 cycle
  78. NOP ;No Operation, padd loop with 1 cycle
  79. NOP ;No Operation, padd loop with 1 cycle
  80. DBNE X, LoopX ;Decrement X and Branch to LoopX if X>0, 3 Cycles
  81. PULX ;Restore X from Stack, 3 Cycles
  82. RTS ;Return from Time Delay Subroutine, 5 Cycles